Module Code - Title:
CE4518
-
COMPUTER ARCHITECTURE
Year Last Offered:
2025/6
Hours Per Week:
Grading Type:
N
Prerequisite Modules:
CE4517
Rationale and Purpose of the Module:
To provide a grounding in the analytic study of computer architecture and an introduction to various architectural styles, e.g., CISC, RISC, and variousnon-von Neumann architectures.
Syllabus:
Review of Von-Neumann architecture: Brief discussion of evolution in processor design from 1940's to today. Computer classifications. Flynn's taxonomy: SISD, SIMD, MIMD.
Computer performance measurement: Execution time and clock cycles per instruction (CPI). MIPs, MFLOPs. Benchmarks: Dhrystone, Whetstone. Kernels: Livermore loops, Linpack, SPECmarks.
Floating point arithmetic: IEEE 754. Addition. Rounding. Denormalised numbers. Multiplication. Iterative division. Precision.
Instruction set design and architecture: Classification. Register machines. Addressing modes. The role of high-level languages and compilers in determining instruction set architecture, "semantic gap", "high-level language architecture", CISC and RISC architectures.
Processor implementation techniques: Datapath. Execution steps. Control: hardwired, microcoded. Handling exceptions.
Pipelining: Hazards in pipelines. CISC and RISC pipelines. Multicycle pipelines (superpipelining). Dynamic scheduling. Scoreboarding. Tomasulo's algorithm. Instruction level parallelism. Superscalar architecture. VLIW. Software pipelining and trace scheduling.
Memory hierarchy design: Register windows. Caches: strategies, replacement policies, block size. Main memory: width, interleaving. Virtual memory: page tables, translation lookaside buffers.
Learning Outcomes:
Cognitive (Knowledge, Understanding, Application, Analysis, Evaluation, Synthesis)
1. Evaluate the impact on CPU performance of instruction set design
2. Evaluate the merits and demerits of various computer performance benchmarks
3. Evaluate the performance characteristics of computer arithmetic algorithms
4. Analyse and compare the performance of various caching algorithms
5. Describe the structure of pipelined and superscalar CPU microarchitectures
Affective (Attitudes and Values)
N/A
Psychomotor (Physical Skills)
N/A
How the Module will be Taught and what will be the Learning Experiences of the Students:
Lectures/Tutorials/Labs
Research Findings Incorporated in to the Syllabus (If Relevant):
Prime Texts:
Hennessy, J.L. & Patterson, D.A. (2007)
Computer Architecture: A Quantitative Approach, 4th ed.
, Elsevier
Patterson, D.A. & Hennessy, J.L. (2005)
Computer Organization & Design, 3rd ed.
, Elsevier
Other Relevant Texts:
Fisher, J.A. Faraboschi, P. & Young C. (2005)
Embedded Computing: A VLIW Approach to ARchitecture, Compilers & Tools
, Elsevier
Shen, J.P. & Lipasti, M.H. (2005)
Modern Processor Design: Fundamentals of Superscalar Processors
, McGraw-Hill
Ercegovac, M.D. & Lang, T. (2004)
Digital Arithmetic
, Elsevier
Stines, J.E. (2004)
Digital Computer Arithmetic Datapath Design Using Verilog HDL
, Kluwer
Lee, S. & Sjoholm, S. (2003)
Design of Computers and Other Complex Digital Devices with VHDL for Designers
, Prentice Hall
Koren, I. (2002)
Computer Arithmetic Algorithms, 2nd ed.
, A K Peters Ltd
Shriver, B. & Smith, B. (1998)
The Anatomy of a High-Performance Microprocessor
, IEEE Computer Society Press
Programme(s) in which this Module is Offered:
Semester(s) Module is Offered:
Module Leader:
Colin.Flanagan@ul.ie