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Module Code - Title:

EE4523 - DIGITAL SYSTEMS 2

Year Last Offered:

2025/6

Hours Per Week:

Lecture

2

Lab

2

Tutorial

0

Other

0

Private

6

Credits

6

Grading Type:

N

Prerequisite Modules:

Rationale and Purpose of the Module:

The module covers digital system topics including: Fully synchronous systems; Finite State Machines(FSM); Mealy and Moore type FSMs; Hardware Description Languages and RTL modelling. Modern digital design requires designers to use HDLs for design and verification. (Digital Systems 1 on the programme is a prerequisite for this module.)

Syllabus:

Fully synchronous systems: A review of the benefits of a fully synchronous system. Finite State Machines(FSM): State diagram, state table and assignments. Mealy and Moore type FSMs. Using memory in a general Mealy-Moore state machine. Other approaches: 'One-shot' encoding and shift register-based machines. Hardware Description Languages: The nature and use of HDLs. Hierarchical modelling concepts and structural specification of logic circuits. Gate-level modelling. Behavioural modelling. Description of basic digital circuits using a HDL. Simulation: Event-driven simulation. Simulation using test benches. Register-Transfer-Level (RTL) description. Design flow and CAD tools. HDL code for FSMs (E.g. serial multiplier).

Learning Outcomes:

Cognitive (Knowledge, Understanding, Application, Analysis, Evaluation, Synthesis)

Draw state diagrams, implement next state functions, and design and implement finite state machines using basic logic elements. Design basic digital circuits/systems using a HDL. Use CAD tools to design and analyse digital systems. Detail how a Hardware Description Language is interpreted for simulation and synthesis Code a test bench to test and verify the operation of a digital circuit Implement and test a FSM using a HDL

Affective (Attitudes and Values)

N/A

Psychomotor (Physical Skills)

N/A

How the Module will be Taught and what will be the Learning Experiences of the Students:

Module will be delivered using 2 hour labs, using industry standard EDA tools. Assessment will include online quizzes, lab exam and project work

Research Findings Incorporated in to the Syllabus (If Relevant):

Prime Texts:

Palnitakar (2003) Verilog HDL: A guide to digital design and synthesis, 2nd Ed, , PrenticeHall.

Other Relevant Texts:

Programme(s) in which this Module is Offered:

BEECENUFA - ELECTRONIC AND COMPUTER ENGINEERING

Semester(s) Module is Offered:

Autumn

Module Leader:

Richard.Conway@ul.ie